Semiconductor device and method of manufacturing the same

• Main Author: ASHIDA MOTOI,TERADA TAKASHI
• Format: Patent
• Language: Chinese; English
• Published: 01.09.2004
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

本发明提供采用使连接N+活性区与P+活性区的布线和栅电极在平面上看重叠来减少占有面积的CMOS晶体管的结构的半导体装置。半导体衬底的表面内，n沟道MOS晶体管的N+活性区(1)与p沟道MOS晶体管的P+活性区(2)通过离子注入形成。在N+活性区(1)与P+活性区(2)上形成栅电极(3)。在栅电极(3)上，形成硅氮化膜的绝缘膜(4)与绝缘膜(5)。在该栅电极(3)上，用CVD等方法形成硅氧化膜的层间绝缘膜(6)。在层间绝缘膜(6)上，形成用以埋入连接N+活性区(1)与P+活性区(2)的布线的开口部(7)。在所形成的开口部(7)内埋入铝等的金属膜，形成埋入布线(8)。 A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.