Method and apparatus for pipelining ordered input/output transactions in a cache coherent multi-processor system

一种用于在一个分布式存储器、高速缓存相干、多处理器系统中把有序的输入/输出事务流水线处理到相干存储器的方法。一个预取引擎响应于一个来自一条输入/输出总线、送往一个分布式、相干存储器的事务从该分布式、相干存储器中预取数据。一个输入/输出相干高速缓存缓冲器接收该预取的数据并且保持和该分布式相干存储器以及在该系统中的其它高速缓存代理相干。 An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-proce...

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Bibliographic Details
Main Authors A. KUMAR, L. LOOI, K. CRETA
Format Patent
LanguageChinese
English
Published 21.01.2004
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:一种用于在一个分布式存储器、高速缓存相干、多处理器系统中把有序的输入/输出事务流水线处理到相干存储器的方法。一个预取引擎响应于一个来自一条输入/输出总线、送往一个分布式、相干存储器的事务从该分布式、相干存储器中预取数据。一个输入/输出相干高速缓存缓冲器接收该预取的数据并且保持和该分布式相干存储器以及在该系统中的其它高速缓存代理相干。 An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.
Bibliography:Application Number: CN20018017309