Semiconductor storaging device for shortening test time

A VBL generation circuit which normally outputs an equalizing potential outputs a potential corresponding to writing data in the test mode and this potential is collectively supplied to the bit lines by an equalizing circuit. In the test mode, a row decoder collectively activates the selected word l...

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Bibliographic Details
Main Author ITO TAKA
Format Patent
LanguageEnglish
Published 14.08.2002
Edition7
Subjects
ELECTRICITY
INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
STATIC STORES
TESTING
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Summary:A VBL generation circuit which normally outputs an equalizing potential outputs a potential corresponding to writing data in the test mode and this potential is collectively supplied to the bit lines by an equalizing circuit. In the test mode, a row decoder collectively activates the selected word lines by setting the pre-decode signals RX0 to RX3 to the active condition and by controlling the pre-decode signals X0 to X3 in accordance with the test signal. Accordingly, a writing in of a test pattern, wherein the detection of a short circuit between the storage nodes of memory cells is possible, can be carried out rapidly.
Bibliography:Application Number: CN20011032592