Polishing pad for semiconductor substrate

A polishing pad for polishing a semiconductor wafer which includes an open-celled, porous substrate having sintered particles of synthetic resin. The porous substrate is a uniform, continuous and tortuous interconnected network of capillary passage. The pores of the porous substrate have an average...

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Bibliographic Details
Main Authors SRIRAM P. ANJUR, K. SEVILLA, FRANK B. KAUFMAN, ROLAND
Format Patent
LanguageEnglish
Published 10.10.2001
Edition7
Subjects
ADHESIVES
BASIC ELECTRIC ELEMENTS
CHEMISTRY
DRESSING OR CONDITIONING OF ABRADING SURFACES
DYES
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
GRINDING
MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING
MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FORELSEWHERE
METALLURGY
MISCELLANEOUS APPLICATIONS OF MATERIALS
MISCELLANEOUS COMPOSITIONS
NATURAL RESINS
PAINTS
PERFORMING OPERATIONS
POLISHES
POLISHING
SEMICONDUCTOR DEVICES
TOOLS FOR GRINDING, BUFFING, OR SHARPENING
TRANSPORTING
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Summary:A polishing pad for polishing a semiconductor wafer which includes an open-celled, porous substrate having sintered particles of synthetic resin. The porous substrate is a uniform, continuous and tortuous interconnected network of capillary passage. The pores of the porous substrate have an average pore diameter of from about 5 to about 100 microns which enhances pad polishing performance.
Bibliography:Application Number: CN19998010562