Polishing pad for semi-conductor substrate

A polishing pad for polishing a semiconductor wafer which includes an open-celled, porous substrate having sintered particles of synthetic resin. The porous substrate is a uniform, continuous and tortuous interconnected network of capillary passage.

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Bibliographic Details
Main Authors SRIRAM P. ANJUR, ROLAND K. SEVILLA, FRANK B. KAUFMAN
Format Patent
LanguageEnglish
Published 28.06.2000
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
DRESSING OR CONDITIONING OF ABRADING SURFACES
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
GRINDING
MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING
PERFORMING OPERATIONS
POLISHING
SEMICONDUCTOR DEVICES
TOOLS FOR GRINDING, BUFFING, OR SHARPENING
TRANSPORTING
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Summary:A polishing pad for polishing a semiconductor wafer which includes an open-celled, porous substrate having sintered particles of synthetic resin. The porous substrate is a uniform, continuous and tortuous interconnected network of capillary passage.
Bibliography:Application Number: CN19988005585