Level shifter incorporating pulse latch

An integrated circuit is provided comprising a module (20) having a low voltage circuit (1) and a high voltage circuit (2). The low voltage circuit includes a flip-flop, a multiplexer (mx) including a plurality of inputs, a flip-flop data input (D), a flip-flop scan enable (SE) input, and a flip-flo...

Full description

Saved in:
Bibliographic Details
Main Author ROSEN EITAN
Format Patent
LanguageChinese
English
Published 30.08.2024
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
Online AccessGet full text

Cover

More Information
Summary:An integrated circuit is provided comprising a module (20) having a low voltage circuit (1) and a high voltage circuit (2). The low voltage circuit includes a flip-flop, a multiplexer (mx) including a plurality of inputs, a flip-flop data input (D), a flip-flop scan enable (SE) input, and a flip-flop scan input (scan in, SI) input. The low voltage circuit (1) further comprises a transmission gate or pass gate having a gate input electronically connected to the output of the multiplexer (mx) and to a gate output node (n1). A clock circuit (22) is for receiving a common clock (CP) signal and has an output terminal (ck) and an inverted output terminal (ckb) of the output terminal. A plurality of inputs are electronically connected to the output clock terminal (ck) and another of the at least one input is electronically connected to the reverse output terminal (ckb). The high voltage circuit (2) comprises a level switching circuit (24), the level switching circuit (24) further comprising a clock switching input e
Bibliography:Application Number: CN20228089636