Failure analysis positioning method for short circuit structure

The invention provides a failure analysis positioning method for a short circuit structure. A semiconductor structure comprises a first layer of metal wire structure and a second layer of metal wire structure located above the first layer of metal wire structure. The first-layer metal wire structure...

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Bibliographic Details
Main Authors YANG LINGYE, GAO JINDE
Format Patent
LanguageChinese
English
Published 23.08.2024
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:The invention provides a failure analysis positioning method for a short circuit structure. A semiconductor structure comprises a first layer of metal wire structure and a second layer of metal wire structure located above the first layer of metal wire structure. The first-layer metal wire structure and the second-layer metal wire structure are connected through a first-layer metal through hole located between the first-layer metal wire structure and the second-layer metal wire structure; the second-layer metal through hole is positioned above the second-layer metal wire structure and is connected with the second-layer metal wire structure; rough positioning of VC abnormity is carried out on the semiconductor structure, and a failure area is found out; plating a conductive material layer on the failure area, and connecting the second layer of metal through hole with the conductive material layer; performing focused ion beam sample preparation along the failure area to form a sample, and observing the cross se
Bibliography:Application Number: CN202310152460