Composite trench gate silicon carbide VDMOS preparation method capable of improving gate reliability

• Main Authors: ZHANG YUJIE, SHI GUANGYAN, ZHANG CHANGSHA, LI YUNJI
• Format: Patent
• Language: Chinese; English
• Published: 20.08.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention provides a preparation method of a composite trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) capable of improving gate reliability, which comprises the following steps of: depositing metal on one side surface of a silicon carbide substrate to form a drain metal layer, and depositing and growing a drift layer on the other side surface of the silicon carbide substrate; depositing a barrier layer above the drift layer, and performing etching and ion implantation to form a well region, an N-type source region and a P-type source region; removing the original barrier layer, forming a barrier layer again, etching, depositing metal, and forming a source metal layer; removing the original barrier layer, re-forming the barrier layer, etching the barrier layer and the drift layer, respectively forming a through hole and a groove, firstly depositing in the groove to form a high-K dielectric layer, and then depositing to form a first gate dielectric layer; according to