Memory controller and memory system

A memory controller and a memory system are provided. A memory controller comprising a processor and configured to control a memory module comprising a plurality of data chips and at least one parity chip, the memory controller comprising an error correction code engine comprising an error correctio...

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Bibliographic Details
Main Authors KIM JI-HO, KANG SUNG-MOOK, LEE KI-JUN, SOHN KYO-MIN, LEE MYUNG-KYU
Format Patent
LanguageChinese
English
Published 20.08.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory controller and a memory system are provided. A memory controller comprising a processor and configured to control a memory module comprising a plurality of data chips and at least one parity chip, the memory controller comprising an error correction code engine comprising an error correction code decoder for correcting Q symbol errors in a set of codewords read from the memory module, q is the largest natural number equal to or less than P, and P is a natural number equal to or greater than four. The error correction code decoder is configured to generate a syndrome including first to Pth syndrome symbols based on the read codeword set by using a parity check matrix, and performing a first error correction code decoding to correct a single symbol error in the read codeword set based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second to Pth syndrome symbols. 提供了存储器控制器和存储器系统。存储器控制器，包括处理器，并且被配置为控制包括多个数据芯片和至少一个奇偶校验芯片的存储器模块，存储器控制器包括纠错码引擎，纠错码引擎包括纠错码解码器，纠错码解码器用于校正
Bibliography:Application Number: CN202311333152