Latch-up effect protection process capable of being used at 200 DEG C

• Main Author: LI YUNSHENG
• Format: Patent
• Language: Chinese; English
• Published: 16.08.2024
• Subjects: BASIC ELECTRIC ELEMENTS; CLEANING; CLEANING IN GENERAL; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY; PERFORMING OPERATIONS; PREVENTION OF FOULING IN GENERAL; SEMICONDUCTOR DEVICES; STATIC ELECTRICITY; TRANSPORTING; WORKING CEMENT, CLAY, OR STONE; WORKING STONE OR STONE-LIKE MATERIALS

The invention discloses a latch-up effect protection process capable of being used at 200 DEG C. The latch-up effect protection process comprises the following process steps: S1, firstly heating sand, separating silicon and carbon monoxide from the sand, continuously heating until high-purity electronic-grade silicon is generated, melting the high-purity silicon into liquid, cooling and solidifying to form a silicon ingot through a Czochralski method, cutting off two ends of the cast ingot by using a diamond saw, and then cutting the cast ingot into slices; breakdown of the latch effect protection structure of the chip body caused by drilling processing is avoided, the situation that the latch resistance of a CMOS circuit is reduced due to the fact that the beta value is increased along with the temperature when the temperature of the chip rises is avoided, scratches and pollution to the surface of the chip are prevented when chippings overflow during drilling, a chip wafer cannot transmit electrostatic charg