Verification of non-overlapping transactions described by assertions for sequential implication

Validation of non-overlapping transactions described by assertions for sequential implication is provided. An assertion for an order implication for a circuit design is received, the order implication defining non-overlapping transactions in which new transactions are not allowed while existing tran...

Full description

Saved in:
Bibliographic Details
Main Authors KUDRYAVTSEV IGOR, SPRAY NIGEL Y, KONY, DAVID
Format Patent
LanguageChinese
English
Published 13.08.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:Validation of non-overlapping transactions described by assertions for sequential implication is provided. An assertion for an order implication for a circuit design is received, the order implication defining non-overlapping transactions in which new transactions are not allowed while existing transactions are still pending. The assertion is converted into a deterministic finite automaton on a finite word in a machine readable form, the deterministic finite automaton being usable to verify the operation of the circuit design. 提供了对由针对顺序蕴涵的断言描述的非重叠事务的验证。接收用于电路设计的针对顺序蕴涵的断言，顺序蕴涵限定非重叠事务，在非重叠事务中，在现有事务仍待决时，新事务不被允许。将该断言转换为机器可读形式的有限字上的确定性有限自动机，该确定性有限自动机可用于验证电路设计的操作。
Bibliography:Application Number: CN202410177613