Preparation method of separated planar gate low-resistance silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor)

• Main Authors: ZHANG CHANGSHA, CHEN TONG, LI YUNJI, YANG GUANGRUI
• Format: Patent
• Language: Chinese; English
• Published: 09.08.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention provides a preparation method of a separated planar gate low-resistance silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor), which comprises the following steps of: depositing metal on one side surface of a silicon carbide substrate to form a drain metal layer, and depositing and growing on the other side surface of the silicon carbide substrate to form a drift layer; depositing a barrier layer above the drift layer, and performing etching and ion implantation to form a low-resistance structure layer, a well region and a source region; removing the original barrier layer, forming a barrier layer again, etching to form a through hole, and performing metal deposition on the through hole to form a source metal layer; removing the original barrier layer, forming a barrier layer again, etching, and depositing to form a gate dielectric layer; the original barrier layer is removed, the barrier layer is formed again, etching and metal deposition are carried out, a gate metal layer