Two-dimensional self-alignment to backside power rail backside via (VBPR)
A semiconductor structure includes a field effect transistor (FET) including a first source-drain region, a second source-drain region, a gate between the first source-drain region and the second source-drain region, and a channel region below the gate and between the first source-drain region and t...
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Main Authors | , , , , |
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Format | Patent |
Language | Chinese English |
Published |
02.08.2024
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Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor structure includes a field effect transistor (FET) including a first source-drain region, a second source-drain region, a gate between the first source-drain region and the second source-drain region, and a channel region below the gate and between the first source-drain region and the second source-drain region. Also included is a front-side wiring network on the front side of the field effect transistor having a plurality of front-side wirings; a front conductive path electrically interconnecting one of the front wirings with the first source-drain region; a backside power rail on a backside of the FET; and a back contact electrically interconnecting the back power rail and the second source-drain region. A dielectric liner and a backside dielectric filler are adjacent to the backside contact on the backside of the gate, and they electrically limit the backside contact in a cross-gate direction.
一种半导体结构包括场效应晶体管(FET),该场效应晶体管包括第一源极-漏极区、第二源极-漏极区、在第一源极-漏极区和第二源极-漏极区之间的栅极、以及在栅极下方并且在第一源极-漏极区和第二源极-漏 |
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Bibliography: | Application Number: CN202280084926 |