Processors, methods, systems, and instructions for atomically storing data wider than native supported data width to memory

• Main Authors: BRYANT, CRAIG, D, BRANDT JASON W, SHANBHOGUE VEDVYAS, ROBINSON STEPHEN J
• Format: Patent
• Language: Chinese; English
• Published: 30.07.2024
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The processor includes a widest set of data registers corresponding to a given logical processor. Each of the data registers of the widest set has a first width in bits. A decode unit corresponding to a given logical processor is to decode instructions specifying a widest set of data registers and to decode atomic store to memory instructions. The atomic store to memory instruction is to indicate data to have a second width in bit that is wider than the first width in bit. The atomic store-to-memory instruction is to indicate memory address information associated with a memory location. The execution unit is coupled with the decode unit. The execution unit is to atomically store the indicated data to the memory location in response to the atomic store-to-memory instruction. 处理器包括对应于给定逻辑处理器的数据寄存器的最宽集合。最宽集合的数据寄存器的每个具有以位计的第一宽度。对应于给定逻辑处理器的解码单元要解码指定最宽集合的数据寄存器的指令，并且要解码原子存储到存储器指令。原子存储到存储器指令要指示要具有以位计的第二宽度的数据，所述以位计的第二宽度比以位计的第一宽度更宽。原子存储到存储器指令要指示与存储器位置关联的存储器地址信息。执行单元与解码单元耦合。执行单元响应于原子存储到存储器指令，要将指示的数据原子地存储到存储器位置。