Memory cell sensing architecture
The invention relates to a memory cell sensing architecture. An apparatus may include a first set of memory cells coupled with a first plate line and a word line, wherein memory cells in the first set of memory cells may be coupled with a first bit line; and a second set of memory cells coupled with...
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Main Authors | , |
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Format | Patent |
Language | Chinese English |
Published |
26.07.2024
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Subjects | |
Online Access | Get full text |
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Summary: | The invention relates to a memory cell sensing architecture. An apparatus may include a first set of memory cells coupled with a first plate line and a word line, wherein memory cells in the first set of memory cells may be coupled with a first bit line; and a second set of memory cells coupled with a second plate line and the word line, wherein memory cells in the second set of memory cells may be coupled with a second bit line. The apparatus may also include a sensing component having a first node coupled with the first bit line and a first capacitor and a second node coupled with the second bit line and a second capacitor. Further, a set of capacitors may be coupled with two nodes. The capacitor may support regulating a voltage of the node of the sensing component.
本申请案涉及存储器单元感测架构。一种设备可包含:与第一板线和字线耦合的第一组存储器单元,其中所述第一组存储器单元中的存储器单元可与第一位线耦合;以及与第二板线和所述字线耦合的第二组存储器单元,其中所述第二组存储器单元中的存储器单元可与第二位线耦合。所述设备还可包含感测组件,其具有与所述第一位线和第一电容器耦合的第一节点以及与所述第二位线和第二电容器耦合的第二节点。此外,一组电容器可与两个节点耦合。所述电容器可支持调节所述感测组件的所述节点的电压。 |
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Bibliography: | Application Number: CN202410111487 |