Enhancement mode transistor with robust gate and method

• Main Authors: LEVY MICHAEL D, SHARMA SAURABH
• Format: Patent
• Language: Chinese; English
• Published: 14.06.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention relates to an enhancement mode transistor with a robust gate and a method. The disclosed structures include an enhancement mode high electron mobility transistor (HEMT). The HEMT includes a barrier layer having a thick portion positioned laterally between the thin portions and a gate. The gate includes a semiconductor layer (e.g., a P-type III-V semiconductor layer) on the thick portion of the barrier layer and having a thick portion positioned laterally between the thin portions. The gate further includes a gate conductor layer on the semiconductor layer and narrower than a thick portion of the semiconductor layer such that an end wall of the gate is stepped. A thin portion of the barrier layer proximate these end walls minimizes or eliminates charge build-up in the underlying channel layer. To block a current path around the gate, the isolation region may be located below a thin portion of the barrier layer offset from the semiconductor layer. The structure may also include alternating e-mode