Method for reducing cache access delay of racetrack memory

• Main Author: ZHANG TIEFEI
• Format: Patent
• Language: Chinese; English
• Published: 14.06.2024
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention provides a method for reducing the cache access delay of a racetrack memory, which can reduce the cache access delay of an RM magnetic stripe and accelerate the data read-write speed of an RM cache. The method comprises the following steps: S1, dividing each cache group into a fast area and a common area, and storing the size of the current fast area by adopting an interval register; s2, each cache block of the cache group comprises an access counter, and the access counter is used for replacing a default LRU bit of the cache block; the access counter value of each cache block is updated during each hit, and is periodically decreased progressively according to a set time interval; s3, each cache group comprises a strategy register, and the value of the strategy register determines a moving strategy of the RM magnetic stripe of the current cache group; s4, determining the value of a strategy register in the cache group according to the access counter value of each cache block in the fast area; an