Multi-layer flip chip high-flexibility stacking and integrated bonding device and method

• Main Authors: LI LONGQIU, QIAO JIANXIN, SU YUNKANG, LIU DAPENG, SHI HAICHUAN
• Format: Patent
• Language: Chinese; English
• Published: 24.05.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention relates to the technical field of multilayer flip chip stacking and integrated bonding processes. The invention relates to a multi-layer flip chip high-flexibility stacking and integrated bonding device, in particular to a multi-layer flip chip high-flexibility stacking and integrated bonding device and a multi-layer flip chip high-flexibility stacking and integrated bonding method. The problems of chip fragmentation or bonding voids caused by improper use of stacking pressure and system dynamic impact caused by rigidity change of a solder structure in a bonding process are solved. The multi-layer chip is subjected to integrated bonding, only one-time heating treatment is carried out in the process of manufacturing the three-dimensional packaging multi-layer chip, the welding spot crack phenomenon caused by repeated high temperature can be reduced, the piezoelectric ceramic driver and the macroscopic displacement table are matched to control the bonding head, and the reliability of the three-dim