Zero power high speed configuration memory

• Main Authors: G.A. ROSENDALE, S. PATHAK, J.E. PAYNE
• Format: Patent
• Language: Chinese; English
• Published: 15.12.2004
• Edition: 7
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

一种存储器件(100)，包含：用于输出比特数据流的单个数据管脚；用于接收时钟脉冲的时钟管脚；组织为多个N比特数据的的存储器阵列(20)，它包含译码器(60，62)用于提供对存储器阵列内存储器位置的访问；在每第N个时钟脉冲时访问存储器位置的装置(32，40，60)；并联的检测电路(66)，用来检测所访问存储器位置的N个比特；使检测电路在一段足以检测存储器位置N个比特的时间内处于使能状态的装置(64)；N比特数据寄存器(42)，用来从检测电路接收N个比特，数据寄存器包含在每个时钟脉冲将一个比特移出的装置；将来自检测电路的N个比特加载入数据寄存器以响应将第N个比特移出数据寄存器的装置(36)；在加电周期内将数据预先加载入数据寄存器的装置(34，44)；因此存储器的数据在将寄存器装置内所包含先前被访问的存储数据的N个比特被移出的同时被访问和检测，存储器访问/检测操作和数据输出操作以流水线方式进行从而使比特流的比特率独立于检测电路的运行速度。 A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.