Storage array, preparation method thereof, memory and electronic equipment

• Main Authors: FAN RENSHI, LIN QI, FANG YICHEN, DING SHICHENG, XU JUNHAO, BU SITONG
• Format: Patent
• Language: Chinese; English
• Published: 07.05.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention discloses a memory array, a preparation method thereof, a memory and electronic equipment. The memory array includes a substrate, a first conductive layer on the substrate, and a transistor array over the first conductive layer. Wherein the first conductive layer comprises a plurality of bit lines which are arranged at intervals, and a first air gap structure is arranged between every two adjacent bit lines; the transistor array comprises a plurality of transistors, each transistor is correspondingly connected with one bit line, and each bit line is connected with at least one transistor in the plurality of transistors. In the memory array, the first air gap structures are arranged between the adjacent bit lines, and the conventional dielectric material is replaced by air with a lower dielectric constant, so that the overall dielectric constant of the dielectric layer can be reduced, the parasitic capacitance of the bit lines is reduced, the RC transmission delay of the bit lines is reduced, the