Stacked chip segmentation method and related device

• Main Authors: LIN SHILIN, MO XIAOLIN, ZHAO YI, LI SHAOBAI, CHEN YUWEN, HU KUNMEI
• Format: Patent
• Language: Chinese; English
• Published: 09.04.2024
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention belongs to the field of data processing, and particularly relates to a stacked chip segmentation method and a related device, and the method comprises the steps: obtaining the data flow information of a to-be-processed chip; the to-be-processed chip comprises a plurality of sub-chips; constructing a chip structure model corresponding to the to-be-processed chip based on the data stream information; each node in the chip structure model corresponds to each sub-chip in the to-be-processed chip; the connection relationship among the nodes in the chip structure model corresponds to the logic dependency relationship among the sub-chips; predicting logic task execution information of the chip structure model in different layout modes through the segmentation decision model to obtain a target layout mode of the to-be-processed chip; and deploying each sub-chip in the to-be-processed chip according to the target layout mode to optimize the layout mode of the to-be-processed chip. According to the method