Implementation method of FPGA computing power dynamic scheduling platform based on PCIe SR-IOV

The invention discloses a PCIe SR-IOV-based FPGA (Field Programmable Gate Array) computing power dynamic scheduling platform implementation method, which comprises the following steps of: 1, establishing vf, 2, binding operators, 3, establishing transmission coordination, designing a unified vf-leve...

Full description

Saved in:
Bibliographic Details
Main Author PENG XUEKUI
Format Patent
LanguageChinese
English
Published 09.04.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:The invention discloses a PCIe SR-IOV-based FPGA (Field Programmable Gate Array) computing power dynamic scheduling platform implementation method, which comprises the following steps of: 1, establishing vf, 2, binding operators, 3, establishing transmission coordination, designing a unified vf-level transmission Ethernet message data segment format protocol, adapting to different types of operator input and output interface data, and 4, establishing a vf-level transmission Ethernet message data segment format protocol. 4, a software platform is established, and the software platform is established on the top layer of the platform and used for providing a user interface, dynamically supervising all vf and dynamically deploying operator resources; according to the method, a flexible computing power dynamic scheduling platform is built through an Ethernet packet data segment format protocol and an FPGA (Field Programmable Gate Array) flow table, a fixed id field is divided in a data segment in an Ethernet packe
Bibliography:Application Number: CN202311722355