NCN resource optimization method on reconfigurable 3D-NTT circuit

• Main Authors: CHEN YI, ZHANG BO, DONG JIN, GUAN ZHENYU, JIA HONGYANG, BIAN SONG, LEI LUCHANG, ZHU YONGQING, HUANG YICHENG, WANG XUEYAN
• Format: Patent
• Language: Chinese; English
• Published: 02.04.2024
• Subjects: ANALOGUE COMPUTERS; CALCULATING; COMPUTING; COUNTING; PHYSICS

The invention discloses an NCN resource optimization method on a reconfigurable 3D-NTT circuit, which is suitable for the reconfigurable 3D-NTT circuit, and comprises the following steps: rearranging input through the reconfigurable 3D-NTT circuit; multiplying an additional twiddle factor introduced by the NCN into a twiddle factor table of the first CT NTT; the extra twiddle factor introduced by the INCN is multiplied to the twiddle factor table of the third GS INTT, so that the second GS NTT module can adjust the point number according to the requirement, and meanwhile, the twiddle factor lacked in the third NTT is multiplied to the coefficient through the two modular multiplication modules. According to the invention, the cost for realizing (I) NCN processing can be effectively reduced, the number of modular multipliers is reduced, and the area and power consumption for realizing (I) NCN by designing a circuit are effectively reduced. 本发明公开了一种在可重构3D-NTT电路上的NCN资源优化方法，适用于一种可重构3D-NTT电路，方法包括：通过可重构3D-NTT电路将输入重新