On-chip cache allocation method of deep neural network multi-core accelerator and related device

• Main Authors: PENG SEN, CAI JINGWEI, WEI YUCHEN, WU ZUOTONG, ZHANG YANNIAN
• Format: Patent
• Language: Chinese; English
• Published: 19.03.2024
• Subjects: CALCULATING; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention provides an on-chip cache allocation method for a deep neural network multi-core accelerator, and the method comprises the steps: determining on-chip cache demands of output features of corresponding layers of nodes at two ends of each edge according to the topological sequence of each layer in a directed acyclic graph and the depth between the corresponding layers of the nodes at the two ends of each edge in the directed acyclic graph; and allocating each on-chip cache demand to an idle cache of each core of the accelerator. By adopting the on-chip cache demand calculation method provided by the invention, the problem of time mismatching in LP mapping can be solved, the utilization rate of the on-chip cache is greatly improved, and the expensive DRAM access times are reduced. The performance and the energy efficiency are improved. Compared with the most advanced open source LP mapping framework Tangram, the on-chip cache allocation method can reduce energy consumption, cost and delay, and remar