Full-bridge packaging structure with multiple chips connected in parallel and packaging method

• Main Authors: MAO JINJIN, HUANG ZHIZHAO, LI JIE, LI YUXIONG, ZHANG JIANXING
• Format: Patent
• Language: Chinese; English
• Published: 15.03.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention relates to the technical field of chip packaging, and particularly discloses a full-bridge packaging structure with multiple chips connected in parallel and a packaging method. The packaging structure comprises a heat dissipation bottom plate, a copper-clad ceramic substrate, a power semiconductor chip, a bonding wire, a driving resistor, a thermistor, positive and negative copper bars, a pouring sealant, a shell and a wiring terminal. A copper-clad ceramic substrate is welded on the heat dissipation bottom plate, and a power semiconductor chip, a thermistor and a wiring terminal are welded on the DBC substrate; and the surface electrode of the power semiconductor chip is electrically connected with the DBC substrate through a bonding wire. According to the packaging structure, through reasonable DBC substrate layout optimization, the packaging module which is compact, compatible with parallel connection of multiple chips, high in reliability, low in stray inductance and uniform in current is ac