Top layer coverage circuit of security chip, security chip and attack identification method

• Main Authors: TANG CAIRONG, WU ZHENGZHONG, ZHANG HUI, LIU ZHE, DENG NENGWEN, ZHANG XIANGSHAN, WANG XIAODONG
• Format: Patent
• Language: Chinese; English
• Published: 06.02.2024
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention provides a top-layer coverage circuit of a security chip, the security chip and an attack identification method. The top-layer coverage circuit of the security chip comprises an inverter unit, an input inverter, an output inverter and a signal comparison circuit, the phase inverter unit comprises at least one stage of phase inverter, the input end of the phase inverter unit is connected with the output end of the input phase inverter, the output end of the phase inverter unit is connected with the input end of the output phase inverter, and all or part of the output ends of the at least one stage of phase inverter and the output end of the output phase inverter are connected with each other. And the signal detection circuit is connected with the input end of the signal comparison circuit. 本发明提供一种安全芯片的顶层覆盖电路、安全芯片及攻击识别方法，安全芯片的顶层覆盖电路包括：反相器单元、输入反相器、输出反相器和信号比对电路；所述反相器单元包括至少一级反相器，所述反相器单元的输入端与所述输入反相器的输出端连接，所述反相器单元的输出端与所述输出反相器的输入端连接，且所述至少一级反相器的全部或部分输出端以及所述输出反相器的输出端，均与所述信号比对电路的输入端连接。