Edge package for high voltage devices
A semiconductor device architecture includes a silicon substrate having sidewalls that are passivated by encapsulating the sidewalls in a dielectric material having a high electric field strength. Encapsulating all sidewalls using high field strength dielectric materials eliminates electrical paths...
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Main Authors | , , , , |
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Format | Patent |
Language | Chinese English |
Published |
09.01.2024
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Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor device architecture includes a silicon substrate having sidewalls that are passivated by encapsulating the sidewalls in a dielectric material having a high electric field strength. Encapsulating all sidewalls using high field strength dielectric materials eliminates electrical paths in air or vacuum, and confines the electric field within these high field strength materials, increasing breakdown voltages relative to unencapsulated devices, and enabling the devices to withstand greater isolation voltages. In some cases, encapsulating the sidewalls in this manner can allow the device to withstand a voltage of 500 V or higher.
半导体器件架构包括具有侧壁的硅衬底,通过将侧壁封装在具有高电场强度的介电材料中而钝化该侧壁。使用高场强介电材料封装所有侧壁消除了空气或真空中的电路径,并且将电场限制在这些高场强材料中,相对于未封装的器件增加了击穿电压,并使器件能够承受更大的隔离电压。在某些情况下,以这种方式封装侧壁能够允许器件承受500V或更高的电压。 |
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Bibliography: | Application Number: CN202280029889 |