ULSL MOS with high dielectric constant insulator and its mfg. method
本发明提供了形成于第一导电类型的半导体基体上的MOS晶体管及其制造方法。该器件包括(a)形成于基体上的界面层;(b)覆盖界面层的高介电常数层,它包括选自Ta#-[2]O#-[5],Ta#-[2](O#-[1-x]N#-[x])#-[5](0<x≤0.6),(Ta#-[2]O#-[5])#-[r]-(TiO#-[2])#-[1-r](r在0.9~1之间)的固溶体,(Ta#-[2]O#-[5])#-[s]-(Al#-[2]O#-[3])#-[1-s](s在0.9~1之间)的固溶体,(Ta#-[2]O#-[5])#-[t]-(ZrO#-[2])#-[1-t](t在0.9~1之间)的固溶体,(Ta#-...
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Main Author | |
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Format | Patent |
Language | Chinese English |
Published |
27.10.2004
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | 本发明提供了形成于第一导电类型的半导体基体上的MOS晶体管及其制造方法。该器件包括(a)形成于基体上的界面层;(b)覆盖界面层的高介电常数层,它包括选自Ta#-[2]O#-[5],Ta#-[2](O#-[1-x]N#-[x])#-[5](0<x≤0.6),(Ta#-[2]O#-[5])#-[r]-(TiO#-[2])#-[1-r](r在0.9~1之间)的固溶体,(Ta#-[2]O#-[5])#-[s]-(Al#-[2]O#-[3])#-[1-s](s在0.9~1之间)的固溶体,(Ta#-[2]O#-[5])#-[t]-(ZrO#-[2])#-[1-t](t在0.9~1之间)的固溶体,(Ta#-[2]O#-[5])#-[u]-(HfO#-[2])#-[1-u](u在0.9~1之间)的固溶体,以及它们的混合物的材料,(c)宽度小于0.3微米,覆盖高介电常数层的栅电极;(d)邻近栅电极的源极区和漏极区;及(e)在高介电常数层上的一对隔离物。
MOS transistor formed on a semiconductor substrate of a first conductivity type and method of fabrication are provided. The device includes (a) an interfacial layer formed on the substrate; (b) a high dielectric constant layer covering the interfacial layer that comprises a material that is selected from the group consisting of Ta2O5, Ta2(O1-xNx)5 wherein x ranges from greater than 0 to 0.6, a solid solution of (Ta2O5)r-(TiO2)1-r wherein r ranges from about 0.9 to less than 1, a solid solution (Ta2O5)s-(Al2O3)1-s wherein s ranges from 0.9 to less than 1, a solid solution of (Ta2O5)t-(ZrO2)1-t wherein t ranges from about 0.9 to less than 1, a solid solution of (Ta2O5)u-(HfO2)1-u wherein u ranges from about 0.9 to less than 1, and mixtures thereof wherein the interfacial layer separates the high dielectric constant layer from the substrate; (b) a gate electrode having a width of less than 0.3 micron covering the high dielectric constant layer; (d) first and second lightly doped regions of a second conductivity type disposed on respective areas of the substrate surface; (e) a source and drain regions of the second conductivity type; and (f) a pair of spacers formed adjacent to the gate electrode and formed on the high dielectric constant layer. The high dielectric layer can be subject to densification. The gate oxide material will significantly improve the performance of an MOS device by reducing or eliminating the current leakage associated with prior art devices. |
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Bibliography: | Application Number: CN19998008151 |