Reconfigurable cache architecture and method for cache coherency

• Main Author: RAZ, ELAD
• Format: Patent
• Language: Chinese; English
• Published: 22.12.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention provides a reconfigurable cache architecture and method for cache coherency. The method includes: receiving a memory access command including at least one address of a memory for access; determining at least one access parameter based on the memory access command, wherein the at least one access parameter comprises at least one of the following: a process ID, a processing core ID, a thread ID and a cache box; calculating a deterministic function on the at least one access parameter and the address to achieve cache coherency; determining a target cache box based in part on calculating a result of the deterministic function, the target cache box to serve the memory access command; the reconfigurable cache architecture is distributed over a plurality of independent physical cache nodes that are electrically coupled to the memory. 本发明提供一种用于缓存一致性的可重构的缓存架构及方法。方法包括︰接收包括一存储器的至少一地址的一存储器存取命令以便进行存取；基于所述存储器存取命令来确定至少一存取参数，其中所述至少一存取参数包括以下至少一种：一进程ID、一处理核心ID、一线程ID及一缓存箱；在所述至少一存取参数及所述地址上计算一确定性函数以达成缓存一致性；部分基于计算所述确