Network-on-chip delay predictor based on artificial neural network

• Main Authors: FU YUXIANG, LI WEI, LI LI, XUE YONGQI, YUAN JIANGTAO, DAI CHENYANG, JI JINLUN, MENG YUAN, ZHAO QIYUE, GAO HENGYUE, HE SHUZHUAN
• Format: Patent
• Language: Chinese; English
• Published: 15.12.2023
• Subjects: CALCULATING; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS; COMPUTING; COUNTING; PHYSICS

The invention discloses an on-chip network delay predictor based on an artificial neural network, which comprises the following steps of: collecting random hardware mapping and a network characteristic value corresponding to the random hardware mapping, and forming a data set by the hardware mapping and the network characteristic value; setting a network structure and training parameters of an on-chip network delay prediction model according to the data set; training the on-chip network delay prediction model by using a K-fold cross validation method to obtain an optimal hyper-parameter of the model; retraining the network-on-chip delay prediction model on all the training data by using the optimal hyper-parameter to obtain a final network-on-chip delay prediction model; and evaluating the generalization ability of the final network-on-chip delay prediction model on the test set. According to the method, an on-chip network simulator can be replaced when the optimal mapping is explored by using exhaustion, heu