Chip connection layer defect detection mechanism and method

• Main Authors: WANG XIAOHONG, ZOU JIAJIA, BAO RUI, WU WENZHI, WANG ZHIHAI, YU KUNPENG, MAO LIANG, HU WANLU
• Format: Patent
• Language: Chinese; English
• Published: 05.12.2023
• Subjects: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES; MEASURING; PHYSICS; TESTING

The invention discloses a chip connection layer defect detection mechanism and method, and belongs to the technical field of chip connection layer defect detection, and the chip connection layer defect detection mechanism comprises an AC impedance analyzer, a voltmeter, a coaxial electrode, a probe and a three-dimensional workbench. Only a simple circuit is needed to measure the voltage between the back gold layer of the chip and the conducting layer of the substrate, and in-situ detection can be carried out without being limited by the spatial position and the geometric dimension of a sample; the disturbance of the defect of the connecting layer on the voltage between the chip back gold layer and the substrate conducting layer is used as a criterion for defect identification, so that the detection result identification is more convenient and accurate. 本发明公开了一种芯片连接层缺陷的检测机构及方法，属于芯片连接层缺陷检测技术领域，包括：交流阻抗分析仪、电压表、同轴电极、探针、三维工作台。本发明仅需要简单电路测量芯片背金层与基板导电层之间的电压，不易受样本的空间位置和几何尺寸限制，即可开展原位检测；将连接层的缺陷对芯片背金层与基板导电层之间电压的扰动作为缺陷识别的判