Method and apparatus for a serial access memory
一种串行存储器件(100)包括一提供预测操作模式的Y解码器(108)以及侦测电路(220-231;720-723;226-231;820-827),其中对目标存储单元的数据侦测是在通过侦测许多可能的存储单元(包括目标单元)的数据线而完全知道其地址前开始的。该方法和设备包括在已按时钟输入一些但非全部地址位时侦测可能的存储单元的第一数据位。在按时钟输入附加地址位时,侦测附加的数据位。在完全接收到目标地址前,侦测其第一数据位将完成,从而可在下一时钟上开始目标存储器的串行输出。此侦测推进特征允许增加内部时钟频率,而不影响各种串行存储器件接口所施加的外部定时约束。 A serial memory dev...
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Main Authors | , , |
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Format | Patent |
Language | Chinese English |
Published |
13.10.2004
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | 一种串行存储器件(100)包括一提供预测操作模式的Y解码器(108)以及侦测电路(220-231;720-723;226-231;820-827),其中对目标存储单元的数据侦测是在通过侦测许多可能的存储单元(包括目标单元)的数据线而完全知道其地址前开始的。该方法和设备包括在已按时钟输入一些但非全部地址位时侦测可能的存储单元的第一数据位。在按时钟输入附加地址位时,侦测附加的数据位。在完全接收到目标地址前,侦测其第一数据位将完成,从而可在下一时钟上开始目标存储器的串行输出。此侦测推进特征允许增加内部时钟频率,而不影响各种串行存储器件接口所施加的外部定时约束。
A serial memory device includes a Y decoder and sensing circuitry which provide a predictive mode of operation, wherein data sensing of a target memory location begins before its address is fully known by sensing the data lines of a number of possible memory locations including the target location. The method and apparatus includes sensing first data bits of possible memory locations when some but not all of the address bits are clocked in. As additional address bits are clocked in, additional data bits are sensed. By the time the target address has been fully received, sensing of its first data bits will have completed so that serial outputting of the target memory can begin on the next clock. This sense-ahead feature permits an increase in the internal clock frequency without affecting external timing constraints imposed by the various serial memory device interfaces. |
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Bibliography: | Application Number: CN19998006066 |