Instructions and logic for sum of absolute differences

In an embodiment, a processor includes: fetch circuitry to fetch instructions, the instructions including a sum of absolute differences (SAD) instruction; the decoding circuit is used for decoding the SAD instruction; and execution circuitry to generate an SAD output vector based on the plurality of...

Full description

Saved in:
Bibliographic Details
Main Authors CHARNEY MARK, AGGARWAL DUSHYANT, VALENTINE ROBERT, ESPIG, MARTIN
Format Patent
LanguageChinese
English
Published 17.11.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:In an embodiment, a processor includes: fetch circuitry to fetch instructions, the instructions including a sum of absolute differences (SAD) instruction; the decoding circuit is used for decoding the SAD instruction; and execution circuitry to generate an SAD output vector based on the plurality of input vectors during execution of the decoded SAD instruction, the SAD output vector comprising a plurality of absolute differences. Other embodiments are described and claimed. 在实施例中，处理器包括：取得电路，该取得电路用于取得指令，该指令包括绝对差总和(SAD)指令；解码电路，该解码电路用于对SAD指令进行解码；以及执行电路，该执行电路用于在经解码的SAD指令的执行期间基于多个输入向量来生成SAD输出向量，该SAD输出向量包括多个绝对差值。其他实施例被描述以及被要求保护。
Bibliography:Application Number: CN202280025004