Real-time fault diagnosis and protection method for EMIF parallel bus

• Main Authors: YU BAOWEI, CHEN MEIZHI, HU LIANGHUI, WANG HAILIANG, CHEN SONG, YANG XIN
• Format: Patent
• Language: Chinese; English
• Published: 24.10.2023
• Subjects: CONTROL OR REGULATING SYSTEMS IN GENERAL; CONTROLLING; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS; PHYSICS; REGULATING

The invention provides a real-time fault diagnosis and protection method for an EMIF (External Memory Interface) parallel bus. The method comprises the following steps: dividing a memory area in an FPGA (Field Programmable Gate Array) into a control word address field and a status word address field; a DSP is utilized to send a DSP write life signal to an FPGA, the FPGA writes the read DSP write life signal into a first preset address of a control word address field to form an FPGA write life signal, generates an FPGA read life signal according to the FPGA write life signal, and stores the FPGA read life signal in a second preset address of a status word address field; a DSP is used for reading the FPGA read life signal to form a DSP read life signal; and performing real-time fault diagnosis according to the DSP write life signal sent by the DSP and the DSP read life signal read by the DSP, and taking a first type of protection measures when a fault is diagnosed. Compared with the prior art, the technical sch