System and method for semiconductor defect guided presintering and system-level testing
Systems and methods for semiconductor defect guided burn-in and system-level testing (SLT) are configured to receive a plurality of in-line defect portion averaging test (I-PAT) scores from an in-line defect portion averaging test (I-PAT) subsystem, where the plurality of I-PAT scores are generated...
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Main Authors | , , , , |
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Format | Patent |
Language | Chinese English |
Published |
20.10.2023
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Subjects | |
Online Access | Get full text |
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Summary: | Systems and methods for semiconductor defect guided burn-in and system-level testing (SLT) are configured to receive a plurality of in-line defect portion averaging test (I-PAT) scores from an in-line defect portion averaging test (I-PAT) subsystem, where the plurality of I-PAT scores are generated by the I-PAT subsystem based on semiconductor die data for a plurality of semiconductor dies, wherein the semiconductor die data includes characterization measurements of the plurality of semiconductor dies, and wherein each I-PAT score of the plurality of I-PAT scores represents a defect rate determined by the I-PAT subsystem based on the characterization measurements of a corresponding semiconductor die of the plurality of semiconductor dies; applying one or more rules to the plurality of I-PAT scores during a dynamic decision process; and generating one or more defect guide placement for at least one of the plurality of semiconductor dies based on the dynamic decision process.
用于半导体缺陷引导预烧及系统级测试(SLT)的系统及方法经配置以:从线 |
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Bibliography: | Application Number: CN202280018257 |