Dynamic link error protection in memory systems

• Main Authors: SRIRAMAGIRI DEEPTI VIJAYALAKSHMI, SUH JUNGWON, ARTIERI ALAIN, CHUN DEXTER TAMIO
• Format: Patent
• Language: Chinese; English
• Published: 20.10.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; INFORMATION STORAGE; PHYSICS; STATIC STORES

The invention relates to dynamic link error protection in a memory system. Errors may be introduced when data is passed through a link between two entities, such as between a host and memory. A link error protection scheme may be implemented to detect and correct errors occurring on the link, thereby enhancing transmission reliability. However, since these protection schemes will increase both latency and power consumption, these benefits are not expensive. In one or more aspects, it is proposed to dynamically adjust the applied link error protection level to match any change in the operating environment. For example, the likelihood of link errors is strongly correlated with link speed. If the link speed is increased, a higher link error protection level may be applied to counteract the increase in link errors. If the link speed is reduced, the protection level may be reduced, so that latency and power consumption penalty may be minimized. 本申请涉及存储器系统中的动态链路差错保护。当数据通过两个实体之间(诸如在主机和存储器之间)的链路传递时，可能引入差错。可实现链路差错保护方案