Processing engine scheduling for time-space partitioned processing systems

• Main Authors: CARVALHO, HUGO, VARADARAJAN, SRIVAZAN, ZAIKOV PAVEL, MILLER LARRY JAMES
• Format: Patent
• Language: Chinese; English
• Published: 10.10.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Embodiments for improved processing efficiency between a processor and at least one co-processor are disclosed. Some examples relate to processor-coprocessor scheduling in which a workload is scheduled to a coprocessor based on a timing window of the processor. In additional or alternative examples, workloads are allocated to the coprocessor based on the processing resources and/or priority order. In connection with the disclosed embodiments, the coprocessor may be implemented by a graphics processing unit (GPU), a hardware processing accelerator, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or other processing circuitry. The processor may be implemented by a central processing unit (CPU) or other processing circuitry. 本发明公开了用于处理器和至少一个协处理器之间的改进处理效率的实施方案。一些示例涉及处理器-协处理器调度，其中工作负载基于该处理器的定时窗口被调度到协处理器。在附加的或另选的示例中，工作负载基于该处理资源和/或优先级顺序被分配到该协处理器。结合所公开的实施方案，该协处理器可由图形处理单元(GPU)、硬件处理加速器、现场可编程门阵列(FPGA)、专用集成电路(ASIC)或其他处理电路实现。该处理器可由中央处理单元(CPU)或其他处理电路实现。