Packaging structure, manufacturing method thereof and terminal equipment

• Main Authors: JIANG SHANGXUAN, ZHAO NAN, JING XIANGMENG, HU XIAO, GENG YUJIE
• Format: Patent
• Language: Chinese; English
• Published: 12.09.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention provides a packaging structure, a manufacturing method thereof and terminal equipment. The problems that die gaps are damaged due to stress generated by CTE mismatch and the like can be solved. The packaging structure comprises a multi-chip assembly. The multi-chip assembly comprises at least two chips and a first wrapping layer wrapping the at least two chips; in addition, the packaging structure further comprises a second wrapping layer, and the second wrapping layer wraps at least part of the side face of the multi-chip assembly. The top of the second wrapping layer is flush with the top of the multi-chip assembly. 本申请提供了一种封装结构及其制作方法、终端设备，能够缓解芯片间(die gap)因CTE失配产生的应力而出现损坏等问题；该封装结构包括多芯片组件；该多芯片组件中包括至少两个芯片以及包裹至少两个芯片的第一包裹层；另外，该封装结构还包括第二包裹层，第二包裹层包裹多芯片组件的至少部分侧面；第二包裹层的顶部与多芯片组件的顶部平齐。