Clock receiving circuit and high-speed analog-to-digital converter

• Main Authors: LIN SHAOBO, LIU XIANGYUAN, LAN YAN, CHEN PEI, LIN TIANJIAO
• Format: Patent
• Language: Chinese; English
• Published: 12.09.2023
• Subjects: AMPLIFIERS; BASIC ELECTRONIC CIRCUITRY; CODE CONVERSION IN GENERAL; CODING; DECODING; ELECTRICITY; PULSE TECHNIQUE

The invention provides a clock receiving circuit and a high-speed analog-to-digital converter. The clock receiving circuit comprises a self-biased differential amplification circuit used for converting a differential sinusoidal signal into a single-ended square wave clock signal; the latch is used for converting the single-ended square wave clock signal into a differential square wave clock signal; the differential frequency halving circuit is used for converting the differential square wave clock signal into a frequency clock signal; the input end of the self-biased differential amplification circuit is connected with a signal source end, the output end of the self-biased differential amplification circuit is connected with the input end of the latch, the output end of the latch is connected with the input end of the differential frequency-halving circuit, and the output end of the differential frequency-halving circuit is connected with the input end of the non-overlapping clock circuit in the ADC; the cloc