Low voltage differential signaling transmitter circuit

• Main Authors: GARG PANKAJ, KAUSHIK SHAILENDRA
• Format: Patent
• Language: Chinese; English
• Published: 29.08.2023
• Subjects: BASIC ELECTRONIC CIRCUITRY; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; PULSE TECHNIQUE

The invention relates to a low voltage differential signaling transmitter circuit. A low voltage differential signal (LVDS) transmitter includes a driver circuit having a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between the first node and the first output. The second transistor is coupled between the first node and the second output. A third transistor is coupled between the first output and the second node. A fourth transistor is coupled between the second output and the second node. A first resistor is coupled between the first output and the common mode node. A second resistor is coupled between the second output and the common mode node. The pre-driver circuit generates a gate control signal that controls the first, second, third, and fourth transistors in response to a data signal. The controlled timing delay is applied to the timing of the logic state transistor of the control signal. 本公开涉及低电压