Packaging interconnection structure, preparation method and electronic system

• Main Authors: HUANG YINGZHUO, JIANG XUEMING, LIN PENGRONG, GUO HENGTONG, WANG YONG, XU SHIMENG, XIE XIAOCHEN
• Format: Patent
• Language: Chinese; English
• Published: 25.08.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention relates to a packaging interconnection structure, a preparation method and an electronic system, the structure comprises a substrate, a bridging chip, an intermediate layer chip set and a top layer chip set, the substrate is internally provided with a groove body, the bridging chip is embedded in the groove body, a wiring layer is distributed on the upper layer of the bridging chip to realize interchip interconnection of the intermediate layer chip set, and the top layer chip set is embedded in the groove body. The upper layer and the lower layer of the interposer chip set are provided with wiring layers, the top chip set realizes inter-chip interconnection through the upper layer wiring of the interposer chip set, and the edge and the substrate are interconnected to realize power supply and signal transmission; the preparation method comprises the steps that the interposer chips are recombined, then the bridge chips are connected with the interposer chip set, then the module is inversely instal