Instruction caching and operating method, processor core and instruction processing method

• Main Authors: HU SHIWEN, ZHAO CHUNYAO
• Format: Patent
• Language: Chinese; English
• Published: 22.08.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The embodiment of the invention provides an instruction caching and operating method, a processor core and an instruction processing method. The instruction cache comprises a plurality of groups, each group comprises a plurality of cache items respectively corresponding to a plurality of paths and a redundancy identification field, and each cache item is configured to store object instruction data and address information of the object instruction data; the redundancy identification field is configured to identify which item of the plurality of cache items stored in the object data is considered to be redundant. According to the instruction cache, the redundancy of the micro instruction cache and the instruction cache is reduced, the effective capacity of the instruction cache is improved, and finally the overall performance of a CPU core is improved. 本公开的实施例提供了一种指令缓存及操作方法、处理器核及指令处理方法。该指令缓存包括多个组，其中，每个组包括分别对应于多个路的多个缓存项以及冗余标识字段，每个缓存项配置为存储对象指令数据以及对象指令数据的地址信息，冗余标识字段配置为用于标识多个缓存项中至少哪一项中存储的对象数据被认为是冗余的。该指令缓存降低微指令缓存与指令