Layout structure of semiconductor device

• Main Authors: WANG HUANCHEN, CHEN XING, ZHANG ZHEN
• Format: Patent
• Language: Chinese; English
• Published: 14.07.2023
• Subjects: BASIC ELECTRIC ELEMENTS; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; PHYSICS; SEMICONDUCTOR DEVICES

The invention provides a semiconductor device layout structure, which comprises a first interconnection pattern layer, a second interconnection pattern layer to an nth interconnection pattern layer, and is characterized in that the first interconnection pattern layer comprises at least two first redundant metal patterns, a third redundant metal pattern and a fourth redundant metal pattern which are positioned in a redundant pattern region; each of the second interconnection pattern layer to the nth interconnection pattern layer comprises at least two second redundant metal patterns, a third redundant metal pattern and a fourth redundant metal pattern which are positioned in the redundant pattern region; the areas of the third redundant metal pattern, the fourth redundant metal pattern and the second redundant metal pattern are different, the shapes of the fourth redundant metal pattern and the second redundant metal pattern are different, and the shapes of the fourth redundant metal pattern and the third redu