Isolation trench and process method

• Main Authors: ZHANG MIN, WU JIA, ZHANG MAOTIAN, WANG GANGNING
• Format: Patent
• Language: Chinese; English
• Published: 11.07.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention discloses an isolation trench which is composed of a first trench located on the surface layer of a semiconductor substrate and a second trench located at the bottom of the center of a shallow trench, and an opening of the second trench is located at the bottom of the first trench; the first groove is a shallow groove, and the second groove is a deep groove; the first groove and the second groove are connected into a whole, are attached to the inner walls of the first groove and the second groove through dielectric layers, and then are filled with polycrystalline silicon to form an isolation structure; the transverse width of the first groove is less than 10 microns, the depth of the first groove is 3000-5000, and the depth of the second groove is 2-5 microns; and the bottom of the second groove is also provided with an injection region. According to the structure, the gain coefficient of the parasitic triode can be greatly reduced, so that the transverse distance between an NPN device and a PNP