Method for improving etching residue of peripheral circuit region after grinding of word line polycrystalline silicon layer

• Main Authors: LI ZHIGUO, WU ZHITAO, XU JIE, JIANG YANGFAN, LIU ZHIBIN, SUN JIAN, WANG DAXIAN, YANG WENGUANG, YU PENG, HAN XIAOHU
• Format: Patent
• Language: Chinese; English
• Published: 30.05.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention provides a method for improving etching residues of a peripheral circuit area after grinding of a word line polycrystalline silicon layer, and the method comprises the steps: S1, providing a substrate which is divided into a core area and a peripheral area, forming a plurality of flash memory gate structures on the substrate, and forming a plurality of word line polycrystalline silicon on the core area; s2, forming a sacrificial layer on the substrate; s3, forming a photoresist layer on the substrate, and exposing the peripheral region; s4, implementing wet etching until the control gate in the flash memory gate structure in the peripheral region is exposed; step S5, removing the photoresist layer; and S6, performing dry etching until the gate oxide layer in the flash memory gate structure in the peripheral region is exposed. According to the method, the hard mask layer with non-uniform surface flatness in the flash memory gate structure is removed through wet etching, and then the control gate,