Ultra-high voltage resistor with voltage sensing
A semiconductor device includes: an active region; a LOCOS region formed within the active region and extending vertically over a top surface of the active region; a gate region formed over the top surface of the active region; and a polysilicon resistor, a bottom surface of the polysilicon resistor...
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Main Authors | , , |
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Format | Patent |
Language | Chinese English |
Published |
05.05.2023
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Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor device includes: an active region; a LOCOS region formed within the active region and extending vertically over a top surface of the active region; a gate region formed over the top surface of the active region; and a polysilicon resistor, a bottom surface of the polysilicon resistor being vertically offset from and physically isolated from a top surface of the LOCOS region. The active region includes a source region disposed laterally from the gate region, a drain region disposed laterally from the gate region, and a drift region disposed laterally between the gate region and the drain region. The polysilicon resistor is formed over the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.
一种半导体装置包括:作用区域;LOCOS区域,所述LOCOS区域形成在所述作用区域内并在所述作用区域的顶部表面上方垂直延伸;栅极区域,所述栅极区域形成在所述作用区域的所述顶部表面上方;以及多晶硅电阻器,所述多晶硅电阻器的底部表面从所述LOCOS区域的顶部表面垂直偏移并与所述顶部表面物理隔离。所述作用区域包括从所述栅极区域横向设置的源极区域、从所述栅极区域横向设置的漏极区域和横向设置在所述栅极区域与所述漏极区域之间的漂移区域。所述多晶硅电阻器形成在所述漂移区域 |
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Bibliography: | Application Number: CN202180057019 |