Hardware-software co-designed multicast for in-memory computing architecture

• Main Authors: JAIN SAURABH, OMAR OM GEE, THIAGARAJAN ANIRUDH, PILLAI KAMLESH R, KALSI GUPREET SINGH, SREENIVAS. SUBRAMONY, ABU HAZRA AVSHAY
• Format: Patent
• Language: Chinese; English
• Published: 05.05.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention relates to hardware-software co-designed multicast for an in-memory computing architecture. A memory architecture includes processing circuitry co-located with a memory subarray for performing computations within the memory architecture. The memory architecture includes a plurality of decoders in a plurality of hierarchical levels, the decoders including multicast capabilities to distribute data or computing operations to respective sub-arrays. Multicast may be configured for each fan-out at each hierarchical level. The compute workflow may be organized into compute supertiles that represent one or more "supertiles" of input data to be processed in the compute supertiles. Each data tile of the input data supertiles may be used by a plurality of compute tiles executed by the processing circuitry of the array, and the data tiles are multicast to the respective processing circuitry for efficient data loading and parallel computing. 本申请涉及用于存储器内计算体系结构的硬件-软件共同设计的多播。一种存储器体系结构包括与存储器子阵列共位的处理电路，用于在存储器体系结构