Hardware logic design hierarchical structure information extraction method and system based on linked list tree

• Main Authors: ZHOU LI, DENG LIN, LIU WEI, TIE JUNBO, TANG XIAO, CHANG QING, LUO LI, ZHOU HAILIANG, TANG SHIWEN, SHI WEI, ZHANG JIANFENG, LIAO HUANQIAN, PAN GUOTENG, FENG QUANYOU, FU WENJIE, GONG RUI, LU HUIHONG, ZHAO WANG
• Format: Patent
• Language: Chinese; English
• Published: 02.05.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses a hardware logic design hierarchical structure information extraction method and system based on a linked list tree, and the method comprises the steps: synthesizing RTL codes of hardware design into a set of netlist files through a synthesis tool, and extracting information in the netlist files, according to the method, the design hierarchical structure information is extracted from a set of hardware module netlist files and organized and stored in a chain table tree mode, input is provided for a logic division algorithm, and the hardware logic design hierarchical structure information based on the chain table tree is obtained. The method has the advantages that hierarchical structure information is convenient to extract, and few storage space resources are occupied, and visual display can be carried out, so that FPGA prototype verification system developers can visually understand the hardware logic design hierarchical structure. 本发明公开了一种基于链表树的硬件逻辑设计层次结构信息提取方法及系统，本发明基于链表树的硬件逻辑设计层次结构信