Method for reducing chip Pipeline timestamp bus bit width and application

• Main Authors: WEI JIAN, CHEN CHEN, JIANG ZHEN, YOU SHUHUA
• Format: Patent
• Language: Chinese; English
• Published: 18.04.2023
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; MULTIPLEX COMMUNICATION; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

The invention discloses a method for reducing the bit width of a chip Pipeline timestamp bus, and the method comprises the following steps: when a timestamp capturing module in an in direction captures an M-bit in-direction timestamp, encoding a low-bit N-bit in-direction timestamp of the M-bit in-direction timestamp into a message information bus, N being smaller than M; the timestamp capture module in the out direction sends a capture signal to the clock engine, and the clock engine captures M-bit out-direction timestamps and transmits the M-bit out-direction timestamps to the timestamp conversion module; the timestamp conversion module obtains an M-bit in-direction timestamp through conversion based on an M-bit out-direction timestamp and a low-bit N-bit in-direction timestamp in the message information bus; and a message editing module receives the M-bit in-direction timestamp, and edits the M-bit in-direction timestamp to a predefined position of the message. According to the method, the pipe line bus wi