Method for realizing pin test in FPGA (Field Programmable Gate Array)

• Main Authors: LU ZHOU, QIAN YUXIANG, ZHOU CHUNXIAO
• Format: Patent
• Language: Chinese; English
• Published: 18.04.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses a method for realizing a pin test in an FPGA (Field Programmable Gate Array), which comprises the following steps of: on the basis of a logic function of the FPGA, combining vector data, an edge placement time sequence, a basic signal waveform and a value limited by a minimum voltage and a maximum voltage in an RAM (Random Access Memory) in the FPGA, inputting a logic waveform to a pin, reading a test period and a sampling period in the RAM in the FPGA by the logic function of the FPGA, and reading the test period and the sampling period of the RAM in the FPGA by the logic function of the FPGA. And comparing expected pin output data stored in the RAM with the collected data to realize the comparison of test data, and completing the pin test, the pin test is realized based on the internal logic function of the FPGA, the pin test part of the FPGA main program comprises a test time sequence file and a test command, and the test time sequence file and the test command are stored in the FPG